Advances in technology have allowed manufacturers of integrated circuits to design the circuits with increasingly smaller design elements. The transistors used in digital integrated circuits to create basic design elements such as logic gates, for example, are becoming smaller and smaller. As transistors and design elements become smaller, manufacturers are able to design and build integrated circuits with much higher densities of design elements and, thus, more functionality.
Increasing the density of design elements presents certain challenges. Each design element in a digital circuit, for example, has associated with it a leakage current. Leakage current, as the name implies, is undesired current that flows through a design element. A metal oxide semiconductor field effect transistor (MOSFET), for example, in theory requires no current flow to activate or deactivate. However, the silicon dioxide that functions as gate insulation is not a perfect insulator, and therefore allows some current to seep through as “leakage current.” Although the leakage current associated with a single MOSFET may be as small as a few picoamperes, the combined leakage current of millions of MOSFETs can consume as much as twenty percent of a chip's total power budget. Furthermore, leakage current can vary depending on the temperature of the circuit, increasing rapidly—even exponentially—with the temperature of the circuit, making it more difficult for engineers to account for it. This undesired and fluctuating power consumption can severely impede a designer's ability to maximize circuit efficiency and performance.
One method of controlling the amount of leakage current in digital integrated circuits involves “power gating,” or “switching off” power to design elements that are not in use. FIG. 1 illustrates an exemplary prior art circuit employing power gating, wherein a MOSFET 2 serves as a power gate to a standard logic gate 4, wherein the logic gate 4 may comprise, for example, a series of MOSFETs or other primitive design elements. When the logic gate 4 is not in use, a sleep signal connected to a gate of the MOSFET 2 is asserted to switch the MOSFET “off” and prevent current from flowing to the logic gate 4. Thus, when the sleep signal is asserted current is prevented from flowing to the primitive design elements of the logic gate 4 and, therefore, leakage current is eliminated.
Power gating also presents challenges because the capacity of the gating transistor must be optimized. If the transistor is too big or “wide,” for example, it will occupy an unnecessarily large portion of the available chip area and thus reduce the total number of design elements that may be placed on the chip. Furthermore, the wider the transistor, the higher the leakage current through it, which limits the transistor's effectiveness to reduce leakage current in the power-gated circuit in standby mode. If the gating transistor is too small or “narrow,” it will limit the amount of drive current available to the design elements which could hinder the performance of the chip.
Therefore, a need exists for a method of determining a capacity of a gating transistor such that the transistor is capable of supplying sufficient operating current while occupying a minimal amount of chip area.